PCI Express: Solving Compliance and Validation Challenges for Transmitters and Receivers

with guest speaker Martin Storch

Join Us: Monday, 18th October
14:00 BST / 15:00 CEST

PCI Express I/O bandwidth has doubled every 3 years on average thereby leading to an increased demand for this full duplex high speed bus architecture. As the industry begins deploying the 5.0 revision with a bit rate of 32 GT/s, new trends and guidelines emerge for receiver compliance and validation. 

This webinar will provide an overview of the methods for solving some of the new test and measurement receiver challenges for PCIE® 4.0 at 16.0 GT/s and PCIE 5.0 at 32.0 GT/s.

The key topics covered in this presentation are as follows: 

  • Status of 5.0 specifications including Base, CEM, and the test specifications
  • Key 4.0 Specifications including BASE and CEM and related test specifications
  • Challenges and latest guidelines on 32 GT/s receiver testing from industry experts
    • Nuances of the 32 GT/s stressed eye calibration
    • Handling high loss backchannels with equalization 
    • Thoughts on Rx testing with and without spread spectrum clocking (SSC)
  • Solving validation challenges with a receiver solution from Anritsu & Tektronix

Register For Live Event


Dr Ali Emsia, Tektronix

Ali completed his PhD in optical communication systems and photonics at Technical University of Darmstadt, Germany. He spent more than two years in Fiber-to-the-x industry developing optical receivers for DOCSIS 3.x technology. He introduced new optical return-path receiver for cable headends in 2018. Since 2019 he is with Tektronix and responsible for high-speed serial applications, high-end oscilloscopes and coherent optics.

Martin Storch, Anritsu

Located in Berlin, Germany
1991 Graduated as Master of Computer Science at Technical University of Warsaw
25 Years experience in Test & Measurement
Focus on physical layer signal integrity test solutions
Anritsu EMEA Field AE for high speed electrical and optical solutions since 2018