As high speed I/O device (HSIO) data rates become faster, increased test times and set up complexities troubles design and validation engineers. This gives us the opportunity to introduced a new category of test equipment focusing on ease of use, time to insight at a cost-effective price.
Tektronix TMT4 Margin Tester is a new tool for diagnosing problems at the PCIe physical layer. Simple to set-up and configure, the TMT4 Margin Tester’s targeted Tx/Rx capability quickly captures issues with PCIe Gen 3 and Gen 4 communications on both ends of the link and evaluates the link health of up to x16 Gen 4 links, across all PCIe presets 0-9, in minutes.
Register for this on demand webinar to witness how the TMT4 Margin Tester evaluates the link health of your PCIe designs dramatically faster, easier, and more cost effectively!
Register to Watch!
Presenter
Sharon Lau
Regional Applications Engineer
As our Regional Applications Engineer, Sharon helps fellow engineers accelerate project progress in multiple applications from high speed communication to general purpose electronic test.
Prior to Tektronix, Sharon was an application engineer with Keysight providing technical support for various test tools, ranging from oscilloscopes to AWG and BERT.
She received her Master’s Degree in Engineering from Universiti Teknologi Malaysia (UTM) and Bachelor’s Degree from Universiti Teknikal Malaysia Melaka (UTeM).