Timing jitter is the unwelcome companion of all electrical systems that use voltage transitions to represent timing information. Historically, electrical systems have lessened the ill effects of timing jitter (or, simply “jitter”) by employing relatively low signaling rates. As signaling rates climb above 2 GHz and voltage swings shrink to conserve power, the timing jitter in a system becomes a significant percentage of the signaling interval. Under these circumstances, jitter becomes a fundamental performance limit.
From this webinar, you will:
As Regional Application Engineer, Ai-Heong is responsible for the high speed communication applications and products. Ai Heong was previously a Signal Integrity Engineer with Intel, with working expertise in IBIS modeling, timing simulation & analysis and product electrical validation.
Ai Heong received his Bachelor degree in Mechatronic from University Technology Malaysia. He then continued to earn his Master Degree with Honours from University Science Malaysia. His Thesis in signal integrity simulation and modeling for IC package via TSV process was published in the international conferences.