Analog and digital designers in the computer, semiconductor, and communications industries are facing new challenges as processor clock speeds race beyond multi GHz and back-plane bus and serial link data rates exceed 32 GT/s. These increasing speeds mean reduced circuit margin for jitter and related signal integrity problems.

By using tools that help you rapidly characterize and discover sources of jitter and signal integrity concerns, you can bring new designs to market faster, with more confidence that they operate reliably in today's ultra high-speed environment.

DPOJET is the premiere eye-diagram, jitter, noise, and timing analysis package available for Tektronix real-time oscilloscopes which provides engineers the highest sensitivity and accuracy available in real-time instruments. With comprehensive jitter and eye-diagram analysis and decomposition algorithms, DPOJET simplifies discovering signal integrity concerns and jitter and their related sources in today's high-speed serial, digital, and communication system designs.

This session will equip you with the essential knowledge and skills in mastering Jitter and Timing Analysis making their design more reliable and robust as well as accomplishing their jobs faster and easier with deeper insights. Register today!

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Tan Ai Heong

Tan Ai Heong

Regional Applications Engineer

As Regional Application Engineer, Ai-Heong is responsible for the high-speed communication applications and products.

Ai-Heong was previously a Signal Integrity Engineer with Intel, with working expertise in IBIS modeling, timing simulation & analysis and product electrical validation.

Ai-Heong received his Bachelor degree in Mechatronic from University Technology Malaysia. He then continued to earn his Master Degree with Honours from University Science Malaysia. His Thesis in signal integrity simulation and modeling for IC package via TSV process was published in international conferences.