Physical Layer Characterization of PCI Express 6.0 PAM4 SerDes Designs 

PCI Express 6.0 is a critical and scalable solution for data-intensive markets such as data centers, AI/ML, and high-performance computing. Technology enhancements have demanded this latest low-latency rate of 64 GT/s and drove the January 2022 release of the PCI Express 6.0 Base specification.

Multi-level signaling (PAM4) is defined for the first time along with a low-latency version of forward error correction (FEC), to achieve a line rate of 64 GT/s. 

Join Tektronix in a discussion of the latest Rev 1.0 requirements for validation of a 6.0 capable SerDes including:

  • SNDR and RLM measurements of transmitters
  • Stressed eye calibration required for receiver jitter tolerance-based validation
  • Enhanced and newly defined measurement methods 
  • How to gain crucial insight into the physical layer performance 

Watch now and learn how to bring to light any design limitations limiting risk prior to high-volume manufacturing.

Register for our on-demand webinar


photo of speaker

David Bouse

Principal Technology Lead, Tektronix

David Bouse is a Principal Technology Leader at Tektronix with expertise in high-speed SERDES including transmitter and receiver test methodologies, digital signal processing algorithms for NRZ/PAM4 signaling, clock characterization, and automation software architecture. David represents Tektronix within the PCI-SIG and CXL standard bodies contributing to the Electrical and Serial Enabling groups participating in the Base, CEM, and test specification development. Pathfinding is his specialty for stressed eye calibration techniques and transmitter characterization to advance data rate speed. David leads numerous gold test suites at the PCI-SIG compliance workshops and helps to develop future programs with an emphasis on test and measurement correlation.