How to Solve Key LPDDR5 DRAM Test Challenges

Sign up for our webinar and learn how you can address the design challenges associated with the new LPDDR5 DRAM.

The introduction of 5G promises to take existing smartphones to the next level by enabling 8k video recording, immersive technologies such as VR (virtual reality) and AR (augmented reality), live recording and enhanced gaming experience.  The consequence for designers, however, is a significant increase in data transfer and power efficiency requirements as found in the new LPDDR5 DRAM specification. Higher data transfer rates and faster signal speeds mean complex designs that push the boundaries of signal integrity and require higher performance measurements for compliance, debugging and validation.

During our webinar we will cover key areas critical to fast, efficient, and reliable validation and debugging of LPDDR5 designs, including:

  • What’s New in LPDDR5?
  • Key Features
  • Signal Integrity Validation and Debugging Techniques
  • S-Parameter Validation and De-embedding
  • Probing Considerations

Sign up now to watch this webinar. 



photo of speaker

Saifee Jasdanwala

Memory Solution Marketing Engineer, Tektronix

Saifee Jasdanwala is a marketing engineer for Tektronix’ Wideband Solutions group. Saifee has 8+ years of experience in validating and characterizing high speed DDR interface for mobile, automotive and server applications. He represents Tektronix in JEDEC and is currently responsible for defining Tektronix solutions for the memory market.